Motion estimator LSI for MPEG2 high level standard

Author

Jiang, Li ; Li, Dongju ; Haba, Shintaro ; Honsawek, Chawalit ; Kunieda, Hiroaki

Author_Institution

Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan

fYear

1999

fDate

18-21 Jan 1999

Firstpage

41

Abstract

In this design, a dedicated motion estimation LSI of MPEG2 is presented. Combining the bits truncation adaptive pyramid (BTAP) algorithm with Window-MSPA architecture as well as by using custom cell and full custom design methods the chip size becomes 4.8 mm×4.8 mm with 0.5 μm 2-level-metal CMOS technology. The test chip which works at 41.5 MHz, possesses a search range of ±67 for image size of 1920×1152 and achieves video rate of 30 fields/s

Keywords

CMOS digital integrated circuits; adaptive signal processing; application specific integrated circuits; high definition television; large scale integration; motion estimation; telecommunication standards; 0.5 micron; 41.5 MHz; MPEG2 high level standard; Window-MSPA architecture; bits truncation adaptive pyramid algorithm; chip size; custom cell; full custom design methods; image size; motion estimator LSI; two-level-metal CMOS technology; video rate; Algorithm design and analysis; CMOS technology; Clocks; Design methodology; HDTV; Hardware; Large scale integration; Motion estimation; SDRAM; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Conference_Location

Wanchai

Print_ISBN

0-7803-5012-X

Type

conf

DOI

10.1109/ASPDAC.1999.759705

Filename

759705