Methods of logical functions decomposition for LUT-based FPGA

The increasing popularity of the field programmable gate array (FPGA) has generated a great deal of interest for FPGA design problems. Due to the fact that FPGAs are mainly characterized both by high integration rate and “reprogrammability”, they are useful for complex image processing. However, fast processing is not possible without parallel processing; also traditional integration methods are not sufficient enough. Thus, one possible way is to adapt the processing algorithm to the FPGA architecture and to avoid general methods of schematic description, allowing an easily implantation, but not an optimum partitioning-routing. With this aim, we tried to minimize the number of CLBs (configurable logic block) in the FPGA, to integrate logical functions (addition, multiplication, comparison etc.) dedicated to segmentation, classification, as well as filtering operations. This is done by expressing the whole “architecture-function to integrate” as Boolean constraints