Title :
A Vernier Over Sampling and Alignment technique for Gb/s Serial Communication
Author :
Omote, Kazuyuki ; Shimizu, Katsunori ; Okamura, Jun-ichi
Author_Institution :
THine Electron. Inc., Tokyo
Abstract :
A new circuit technique of deserializing for Gb/s serial communication such as "digital visual interface" for PC and "high-definition multimedia interface" for CE application is proposed. Vernier over sampling and alignment technique can achieve both low power and low bit error rate at high frequency operation in DVI/HDCP digital graphic communication receiver. VOSA circuit is simple and mostly digitally controlled, therefore it is robust and portable. Demonstrating VOSA performance, the circuit was implemented to the DVI digital flat panel communication link receiver as an analog front-end (AFE) with the industry standard 0.25mum CMOS process
Keywords :
CMOS integrated circuits; analogue-digital conversion; computer interfaces; data communication equipment; graphical user interfaces; low-power electronics; receivers; 0.25 micron; DVI; HDCP; analog front-end; digital flat panel communication link receiver; digital graphic communication receiver; digital visual interface; high-definition multimedia interface; serial communication; vernier over sampling and alignment technique; Bit error rate; Circuits; Communication industry; Communication system control; Digital control; Frequency; Graphics; Page description languages; Robust control; Sampling methods;
Conference_Titel :
Asian Solid-State Circuits Conference, 2005
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-9162-4
Electronic_ISBN :
0-7803-9163-2
DOI :
10.1109/ASSCC.2005.251781