A Wide Band CDR for Digital Video Data Transmission

Author

Ozawa, Seiichi ; Miura, Satoshi ; Kousokabe, Seiichi ; Ishizone, Yohei ; Tomosugi, Shinichiro ; Okamura, Jun-ichi

Author_Institution

THine Electron. Inc., Tokyo

fYear

2005

fDate

Nov. 2005

Firstpage

33

Lastpage

36

Abstract

This paper describes a wide band CDR with a new encoding scheme for a digital video data transmission. The CDR works from 105Mbps to 1365Mbps without any external frequency references. The proposed encoding scheme uses both PECT (periodic embedded clock transition) and PECT (periodic embedded clock period) scheme, and it helps the CDR´s capture process. The CDR is using both digital and analog techniques. Digital block adjusts VCO frequency utilizing PECT and PECP scheme, and analog block maintains lock with small jitter. The device is fabricated on 0.35mum standard logic CMOS process

Keywords

CMOS logic circuits; digital video broadcasting; encoding; voltage-controlled oscillators; 0.35 micron; 105 to 1365 Mbit/s; VCO frequency; digital video data transmission; encoding scheme; logic CMOS process; periodic embedded clock period scheme; periodic embedded clock transition scheme; wide band CDR; CMOS logic circuits; CMOS process; Clocks; Data communication; Encoding; Frequency; Jitter; Logic devices; Voltage-controlled oscillators; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Asian Solid-State Circuits Conference, 2005

Conference_Location

Hsinchu

Print_ISBN

0-7803-9163-2

Electronic_ISBN

0-7803-9163-2

Type

conf

DOI

10.1109/ASSCC.2005.251782

Filename

4017524