Title :
A 667MT/s 10.7GB/s Multiprocessor Bus Interface
Author :
Muljono, Harry ; Rusu, Stefan ; Tian, Kathy ; Atha, Mubeen
Author_Institution :
Enterprise Microprocessor Group, Intel Corp., Santa Clara, CA
Abstract :
A 130nm 1.2V GTL bus interface with compensated slew rate and termination achieves 667MT/S 10.7GB/S data rate in a 3-load MP environment. The design utilizes preboost and postboost methods, current steering circuit to minimize simultaneous switching noise and negative hysteresis to speed up the common-clock delay. The design also incorporates system-level I/O loopback for system timing marginality test
Keywords :
integrated circuit noise; logic design; microprocessor chips; multiprocessing systems; system buses; 1.2 V; 10.7 Gbit/s; 130 nm; 3-load MP environment; GTL bus interface; common-clock delay; compensated slew rate; current steering circuit; multiprocessor bus interface; negative hysteresis; postboost methods; preboost methods; simultaneous switching noise; system-level I/O loopback; Atherosclerosis; Delay; Hysteresis; Impedance; Packaging; Reflection; Signal design; Space technology; Timing; Voltage;
Conference_Titel :
Asian Solid-State Circuits Conference, 2005
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-9162-4
Electronic_ISBN :
0-7803-9163-2
DOI :
10.1109/ASSCC.2005.251804
