Title :
An upper-bound algorithm for gate-level delay analysis
Author :
Lu, Sunshin ; Lai, Feipei
Author_Institution :
Dept. of Comput. Sci., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
An upper-bound algorithm for gate-level delay analysis dynamically updates path timing information. When conflicting logic value occurs, the algorithm switches to the most promising path according to the updated path delay. The execution time has been greatly shortened by reducing the number of paths to be traced. The algorithm has been run on ten benchmark circuits. The results show its advantages in efficiency and accuracy over the PERT approach
Keywords :
delays; logic design; logic gates; accuracy; benchmark circuits; efficiency; execution time; gate-level delay analysis; logic value; path timing information; updated path delay; upper-bound algorithm; Algorithm design and analysis; Circuit analysis; Computer science; Delay; Functional analysis; Information analysis; Logic; Performance analysis; Switches; Timing;
Conference_Titel :
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Conference_Location :
Taipei
DOI :
10.1109/VTSA.1989.68620
