Title :
A novel high write speed, low power, read-SNM-free 6T SRAM cell
Author :
Sil, Abhijit ; Ghosh, Soumik ; Gogineni, Neeharika ; Bayoumi, Magdy
Author_Institution :
Center for Adv. Comput. Studies, Univ. of Louisiana at Lafayette, Lafayette, LA
Abstract :
In the nano-scaled technologies, increasing sub-threshold leakage, dynamic power and degrading SNM pose major hurdle for future generation circuits, especially in SRAM arrays. In this paper, a novel high write speed, low power, read-SNM-free 6T SRAM cell is presented. Simulation using 128 times 16 SRAM array in 90 nm CMOS technology shows that the cell can achieve 64% faster write operation than the conventional cell. Experimental results show that the write and read energy of the proposed cell are 76.8% and 53% lesser than the conventional cell respectively. Write precharge energy for the proposed cell is almost 81% less than that of conventional cell. During read operation, the proposed cell does not induce any noise at data nodes (dasiaQpsila & dasiaQbarpsila) which makes it a read-SNM-free design.
Keywords :
CMOS memory circuits; SRAM chips; low-power electronics; nanoelectronics; CMOS technology; dynamic power range; high write speed SRAM cell; low power operation; nanoscaled technologies; read energy; read-SNM-free SRAM cell design; size 90 nm; sub-threshold leakage; write precharge energy; CMOS technology; Circuits; Degradation; Energy consumption; Power dissipation; Power generation; Random access memory; Stability; Subthreshold current; Threshold voltage; Read snm; SRAM; low power; write speed;
Conference_Titel :
Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on
Conference_Location :
Knoxville, TN
Print_ISBN :
978-1-4244-2166-4
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2008.4616913
