An efficient VLSI implementation of DWT for JPEG2000

This paper proposed an efficient VLSI architecture for lifting-based Discrete Wavelet Transformation (DWT) recommended by JPEG2000. The architecture included the basic processing element (PE) and the memory control unit (MCU) and the memory modules. The finite precision analysis has been carried out and the data path width was fixed at 20bis. The memory module included fourteen basic memory units. Ten of them were used to the DWT processing and the residual four units was used to entropy coding. The MCU was in charge of the memory access and set up a pipelining processing between the DWT and entropy coding in JPEG2000. The architecture has default filters to generate an output every cycle for JPEG2000. The architecture has been implemented in behavioral Verilog. The estimated gates of our proposed architecture in SIMC 0.18-/spl mu/m technology are 6600 and the estimated frequency of operation is 300 Mhz.