Title :
SRAM Circuit with Expanded Operating Margin and Reduced Stand-by Leakage Current Using Thin-BOX FD-SOI Transistors
Author :
Yamaoka, Masanao ; Tsuchiya, Ryuta ; Kawahara, Takayuki
Author_Institution :
Central Res. Lab., Hitachi, Ltd., Tokyo
Abstract :
We propose a low-power SRAM circuit using thin-BOX FD-SOI transistors. The SRAM circuit uses back-gate bias effectively, and acquires high operating margin and high speed operation under low supply voltage. The leakage current in standby state is reduced. This SRAM achieves 30% faster writing time under low-voltage operation, and 90% less stand-by power
Keywords :
SRAM chips; leakage currents; low-power electronics; silicon-on-insulator; SRAM circuit; back-gate bias; stand-by leakage current; thin-BOX FD-SOI transistors; Circuits; Controllability; Energy consumption; Fluctuations; Laboratories; Leakage current; Low voltage; Random access memory; Transistors; Writing;
Conference_Titel :
Asian Solid-State Circuits Conference, 2005
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-9162-4
Electronic_ISBN :
0-7803-9163-2
DOI :
10.1109/ASSCC.2005.251677
