A Low Power 128Mb Pseudo SRAM Using Hyper Destructive Read Architecture

A 128Mb pseudo SRAM is developed using a special type of architecture with the purpose of effectively reducing the standby current. Standby current, especially the off leakage current is becoming more difficult problem to handle in modern devices because shorter channel length in high density and high speed devices are at a point where off leakage is the major source. In order to solve this issue, hyper destructive read architecture (HyDRA) is developed. HyDRA is a special DRAM architecture enabling destructive reading of DRAM cells using global bitline and extra tag memory. The paper demonstrates HyDRA utilizing its fast row cycle capability to instead minimize standby power to 150muA @ 2.1V and 90degC while maintaining the speed and chip area of the conventional scheme using the same process technology