Title :
Testing the 400 MHz IBM generation-4 CMOS chip
Author :
Foote, Thomas G. ; Hoffman, Dale E. ; Huott, William V. ; Koprowski, Timothy J. ; Robbins, Bryan J. ; Kusko, Mary P.
Author_Institution :
IBM Corp., Poughkeepsie, NY, USA
Abstract :
This paper describes the design-for-test framework of the 400 MHz CMOS central processor (CP) used in the fourth generation (G4) of the IBM S/390(R) line of servers. It will describe details of modeling logic to achieve correct and effective tests as well as describe the test sets required to test all portions of the design. This includes built-in self-test, array self-test, weighted random pattern generation, algorithmic pattern generation, and manual patterns. Tests are used to detect faults, static and dynamic, and to debug/diagnose chip failures characteristic to the function under test. The described tests ensure the highest reliability for the components within the system and the same test patterns can be applied from manufacturing all the way to the system level
Keywords :
CMOS digital integrated circuits; IBM computers; built-in self test; computer testing; fault diagnosis; integrated circuit testing; logic design; logic testing; microprocessor chips; random-access storage; 400 MHz; CMOS chip; IBM S/390; LBIST; RAM; algorithmic pattern generation; array self-test; design-for-test; failures diagnosis; flush test; modeling; scan test; weighted random pattern; weighted random pattern generation; Built-in self-test; CMOS logic circuits; CMOS process; Design for testability; Fault detection; Logic design; Logic testing; Manufacturing; Semiconductor device modeling; System testing;
Conference_Titel :
Test Conference, 1997. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-4209-7
DOI :
10.1109/TEST.1997.639601
