DocumentCode :
2736717
Title :
A Multimode GSM/DCS/WCDMA Double Loop Frequency Synthesizer
Author :
Badets, Franck ; Camino, Laurent ; Rieubon, Sebastien ; Divel, Thiery ; Cerisier, Patrick ; Dedieu, Sebastien ; Belot, Didier
Author_Institution :
STMicroelectron., Grenoble
fYear :
2005
fDate :
1-3 Nov. 2005
Firstpage :
201
Lastpage :
204
Abstract :
In this paper a WCDMA/GSM/DCS/PCS multimode frequency synthesizer is presented. It consists in a double loop synthesizer with a programmable divider between each integer synthesizer in order to provide fractional steps. The synthesizer has been implemented in a STMicroelectronics 0.25 mum RF BiCMOS technology. Measured phase noise at 400 kHz of the 3.8 GHz carrier is -118 dBc/Hz. Power consumption is about 21 mA from a 2.5 V battery
Keywords :
3G mobile communication; BiCMOS integrated circuits; cellular radio; code division multiple access; frequency synthesizers; phase locked loops; phase noise; transceivers; 0.25 micron; 2.5 V; 21 mA; 3.8 GHz; 400 kHz; DCS; GSM; RF BiCMOS technology; WCDMA; double loop synthesizer; integer synthesizer; multimode frequency synthesizer; programmable divider; Battery charge measurement; BiCMOS integrated circuits; Distributed control; Frequency synthesizers; GSM; Multiaccess communication; Noise measurement; Personal communication networks; Power measurement; Radio frequency;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asian Solid-State Circuits Conference, 2005
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-9162-4
Electronic_ISBN :
0-7803-9163-2
Type :
conf
DOI :
10.1109/ASSCC.2005.251700
Filename :
4017566
Link To Document :
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