An efficient VLSI implementation for the 1D convolutional discrete wavelet transform

This paper presents an efficient implementation of a convolution-based 1D discrete wavelet transform (DWT). The proposed architecture combines several optimizations that improve the performance of the hardware design in terms of throughput and power dissipation. We designed and analyzed the performance of numerous DWT architectures using pertinent metrics and cost functions that assess the impact of the design optimizations. We synthesized our VLSI architectures using a 0.18 mu standard cell library. The final VLSI design combines polyphase decimated FIR filters to reduce power dissipation, pipelined computational cells for higher throughput, and data-interleaving for lower chip area. An analytical comparison with other existing DWT implementations illustrates a two fold improvement in throughput for the proposed architecture.