A MRMDF FFT Processor for MIMO OFDM Applications

Author

Lin, Yu-Wei ; Liao, Wan-Chun ; Lee, Chen-Yi

Author_Institution

Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu

fYear

2005

fDate

Nov. 2005

Firstpage

225

Lastpage

228

Abstract

In this paper, the proposed pipelined FFT processor, which is based on MRMDF structure, can deal with the simultaneous multiple input sequences more efficiently for MIMO OFDM applications. Furthermore, the hardware costs of memory and complex multipliers in our method can be saved by means of delay feedback and data scheduling approaches. The higher-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications. A test chip for 802.11n system has been designed using 0.13mum 1P8M CMOS process with core area of 2142 times 660 mum². Power dissipation is 5.2mW when 128 points FFT with four data streams are calculated

Keywords

CMOS digital integrated circuits; MIMO communication; OFDM modulation; fast Fourier transforms; microprocessor chips; pipeline arithmetic; 0.13 micron; 1P8M CMOS process; 5.2 mW; IEEE 802.11n system; MIMO OFDM; MRMDF FFT processor; complex multiplications; data scheduling; delay feedback; pipelined FFT processor; CMOS process; Costs; Delay; Feedback; Hardware; MIMO; OFDM; Power dissipation; Processor scheduling; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Asian Solid-State Circuits Conference, 2005

Conference_Location

Hsinchu

Print_ISBN

0-7803-9163-2

Electronic_ISBN

0-7803-9163-2

Type

conf

DOI

10.1109/ASSCC.2005.251706

Filename

4017572