Title :
A new current-integrating bang-bang phase detector for clock and data recovery
Author_Institution :
Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON
Abstract :
This paper proposes a new current-integrating bang-bang phase detector that is insensitive to data transient disturbances. The phase detector extracts early-late phase information between the input and retimed data by integrating the input data and its complementary on two identical capacitors. In addition, it employs only one regenerative DFF for phase detection, significantly lowering hardware cost. The phase detector has been implemented in TSMC-0.18 mum 1.8 V CMOS technology and analyzed using Spectre-RF from Cadence Design Systems with BSIM3.3 v device models. Simulation results are presented.
Keywords :
CMOS digital integrated circuits; integrating circuits; phase detectors; synchronisation; BSIM3.3 v device models; CMOS technology; Cadence design systems; Spectre-RF; TSMC technology; binary phase detector; clock-and-data recovery; current-integrating bang-bang phase detector; data transient disturbances; hardware cost reduction; input data integration; regenerative DFF; size 0.18 mum; voltage 1.8 V; CMOS technology; Capacitors; Circuits; Clocks; Data mining; Detectors; Error correction; Hardware; Phase detection; Voltage;
Conference_Titel :
Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on
Conference_Location :
Knoxville, TN
Print_ISBN :
978-1-4244-2166-4
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2008.4616945
