A simplified calibration technique for pipelined ADCs using reference tapering

A new calibration method applicable to pipelined analog-to-digital converters (ADCs) is introduced. The concept of reference tapering is presented as a simplification of a previous method. Behavioral modeling results verify that this simple method is a viable alternative for increasing the performance of ADCs fabricated in deep-submicron processes. For low amplifier gains, simulations show an improvement of as much as 2 effective bits over an un-calibrated pipeline ADC. A prototype chip based on an existing design is currently being implemented as a proof-of-concept of this new invention. Details of this new design are presented.