Single newton-raphson iteration for integer-rounded divider for lattice reduction algorithms

For MIMO transmissions lattice reduction-aided equalizers have emerged as a potential low-complexity method for achieving the same receiver diversity as high-complexity maximum likelihood (ML) detectors. Toward the VLSI implementation of lattice reduction algorithms, we address the integer-rounding operation present in these algorithms. In particular we exploit the reciprocal-reuse of a complex-valued lattice reduction algorithm, the Complex Lenstra, Lenstra, Lovasz (CLLL) algorithm, by employing the reciprocation-based Newton-Raphson iteration technique. We derive an easily-computed upper-bound of the relative quotient error for a given reciprocal table size. In addition we show how the CLLL algorithm contains part of the rounding error detection operations necessary for Newton-Raphson-based methods. Application of this analysis results in an area-efficient hardware architecture for FPGAs that requires a small reciprocal look-up table. Implementation results on both Xilinx Virtex4 and Virtex5 FPGAs show that our approach exhibits slightly smaller average latency and requires 40% less equivalent gates than a comparison architecture constructed from existing IP blocks.