Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme

This paper presents a new footless dual-rail domino circuit that efficiently combines a footless dynamic circuit technique with a robust self-timed precharge scheme for high performance VLSI design. Along with these, the proposed circuit achieves a whole footless dual-rail domino circuit with the use of the proposed separator. A 20-stage NAND chain with fan-out 8 is implemented in 0.15-mum SOI CMOS technology for performance evaluation. Measurement results reveal that the proposed circuit achieves 2.57, 1.72 and 1.12 times speed improvement over the circuit implemented with CPL, the conventional static CMOS and the conventional dynamic DCVSL, respectively