Title :
Single Polysilicon Gate High-Density Logic Using Independently-Controlled Double-Gate Devices
Author :
Chiang, Meng-Hsueh ; Kim, Keunwoo ; Chuang, Ching-Te ; Tretz, Christophe
Author_Institution :
Dept. of Electron. Eng., Nat. Ilan Univ.
Abstract :
Novel double-gate (DG) CMOS logic with a single polysilicon gate process is proposed using independently biased gates. The unique gate-to-gate coupling of DG devices is exploited to improve circuit density, capacitance, performance, and power in 25 nm logic circuits by halving the number of stacked transistors as well as parallel transistors for implementing logic functions. The performance, power, and design trade-offs as well as layouts for logic gates are analyzed via mixed-mode two-dimensional numerical simulations
Keywords :
CMOS logic circuits; logic gates; 25 nm; 2D numerical simulations; DG CMOS logic; DG devices; circuit density; double-gate CMOS logic; gate-to-gate coupling; high-density logic; independently biased gates; independently-controlled double-gate devices; logic circuits; logic functions; logic gates; mixed-mode numerical simulations; parallel transistors; single polysilicon gate process; CMOS logic circuits; CMOS process; Capacitance; Coupling circuits; Logic circuits; Logic design; Logic devices; Logic functions; Logic gates; Performance analysis;
Conference_Titel :
Asian Solid-State Circuits Conference, 2005
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-9163-2
Electronic_ISBN :
0-7803-9163-2
DOI :
10.1109/ASSCC.2005.251738
