DocumentCode
2737472
Title
A Digitally Controlled Oscillator for Low Jitter All Digital Phase Locked Loops
Author
Lee, Kwang-Jin ; Jung, Seung-Hun ; Kim, Yun-Jeong ; Kim, Chul ; Kim, Suki ; Cho, Uk-Rae ; Kwak, Choong-Guen ; Byun, Hyun-Geun
Author_Institution
Dept. of Electron. Eng., Korea Univ., Seoul
fYear
2005
fDate
Nov. 2005
Firstpage
365
Lastpage
368
Abstract
This paper presents a digitally controlled oscillator (DCO) for high speed ADPLLs. The proposed DCO circuit has control codes of thermometer type, which can reduce jitters. Performance of the DCO is verified through a novel ADPLL. The ADPLL chip with the DCO was fabricated using a 0.18mum CMOS technology. The ADPLL has operation range between 520MHz and 1.5GHz and has 76ps peak-to-peak jitter at 668MHz
Keywords
CMOS integrated circuits; digital phase locked loops; jitter; oscillators; 0.18 micron; 0.52 to 1.5 GHz; CMOS technology; control codes; digital phase locked loops; digitally controlled oscillator; jitter reduction; CMOS technology; Circuit optimization; Delay; Digital control; Frequency; Jitter; Oscillators; Phase locked loops; Resistors; Tuning;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Solid-State Circuits Conference, 2005
Conference_Location
Hsinchu
Print_ISBN
0-7803-9163-2
Electronic_ISBN
0-7803-9163-2
Type
conf
DOI
10.1109/ASSCC.2005.251741
Filename
4017607
Link To Document