A Low-Power Dual-Band WLAN CMOS Receiver

Author

Kao, Shiau-Wen ; Kuo, Ming-Ching ; Wang, Chao-Shiun ; Lee, Yi-Bin ; Chen, Chih-Hung ; Su, Peng-Un ; Yang, Tzu-Yi

Author_Institution

SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu

fYear

2005

fDate

Nov. 2005

Firstpage

397

Lastpage

400

Abstract

A dual-band, dual-conversion receiver integrated from LNA to analog baseband circuitry is presented. The low-pass filters integrate a cutoff frequency auto calibration scheme and can be automatically tuned from 6-MHz to 17-MHz with plusmn3% accuracy. This design is suitable for multi-standard, multi-bandwidth applications, such as 802.11a/b/g and the incoming 802.11n, while the RF front-end is shared. The chip was fabricated in TSMC 0.25mum CMOS process with 2.5V power supply. The noise figure is 2.8dB/3.9-dB for 2.4/5-GHz bands at the maximum gain setting, and the IIP3 of 10/-3-dBm is achieved for 2.4/5-GHz bands at the minimum gain. The receiver provides a programmable gain of 88/78-dB in 2dB steps and consumes 51/54-mA current for 2.4/5-GHz bands, respectively

Keywords

CMOS integrated circuits; IEEE standards; low noise amplifiers; low-pass filters; microwave receivers; wireless LAN; 0.25 micron; 2.5 V; 2.8 dB; 3.9 dB; 51 mA; 6 to 17 MHz; 78 dB; 88 dB; CMOS process; IEEE 802.11a/b/g; IEEE 802.11n; LNA; TSMC; WLAN CMOS receiver; analog baseband circuitry; dual-band receiver; low-pass filters; low-power receiver; Baseband; CMOS process; Calibration; Circuits; Cutoff frequency; Dual band; Low pass filters; Power supplies; Radio frequency; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Asian Solid-State Circuits Conference, 2005

Conference_Location

Hsinchu

Print_ISBN

0-7803-9163-2

Electronic_ISBN

0-7803-9163-2

Type

conf

DOI

10.1109/ASSCC.2005.251749

Filename

4017615