A Low Power High Performance Register-Controlled Digital DLL for 2Gbps x32 GDDR SDRAM

Author

Lee, Hyun-Woo ; Yun, Won-Joo ; Kang, Sin-Deok ; Moon, Hyung-Wook ; Kwack, Seung-Wook ; Lee, Dong-Uk ; Kwean, Ki-Chang ; Kim, Kwan-Weon ; Choi, Young-Jung ; Ahn, Jin-Hong ; Kih, Joong-Sik

Author_Institution

Memory R&D Div., Hynix Semicond. Inc., Kyoungki

fYear

2005

fDate

1-3 Nov. 2005

Firstpage

401

Lastpage

404

Abstract

A new low power high performance register-controlled digital delay locked loop (LPRCDLL) is presented. The circuit has fine delay compensation ability, fast delay compensation according to external voltage variation, and inherent duty correction. The digital DLL used for 2Gbps 8M times 32 GDDR3 SDRAM is fabricated using a 0.10mum technology. Experimental results show less than plusmn1% duty correction from external duty error of plusmn5%, less than 400 cycle locking time, 1GHz operation frequency at 1.5V, 38mW at 1.5V/1GHz, and a wide locking range from 250MHz to 1GHz

Keywords

DRAM chips; delay lock loops; delay systems; integrated circuit design; low-power electronics; 0.10 micron; 0.25 to 1 GHz; 1.5 V; 2 Gbit/s; 38 mW; GDDR SDRAM; LPRCDLL; delay compensation; duty correction; high performance digital DLL; low power digital DLL; register-controlled digital DLL; Circuits; Clocks; Control systems; Delay systems; Error correction; Jitter; Moon; Research and development; SDRAM; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Asian Solid-State Circuits Conference, 2005

Conference_Location

Hsinchu

Print_ISBN

0-7803-9162-4

Electronic_ISBN

0-7803-9163-2

Type

conf

DOI

10.1109/ASSCC.2005.251750

Filename

4017616