Title :
A 2.5Gbps Burst-Mode Clock and Data Recovery Circuit
Author :
Liang, Che-Fu ; Hwu, Sy-Chyuan ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., National Taiwan Univ., Taipei
Abstract :
A 2.5Gbps burst-mode CDR circuit is fabricated in 0.18mum CMOS process. The data generator for this CDR circuit is presented with reduced hardware and low power dissipation. The tight timing budget of the clock generator is also relaxed. The bit error rate less than 10-12 is achieved for a PRBS of 231-1 with 500ppm frequency deviation. The area of the digital core is 0.36mm2 and the power of 33mW/port is achieved for a 1.8V supply
Keywords :
CMOS digital integrated circuits; binary sequences; clocks; error statistics; phase locked loops; random sequences; synchronisation; 0.18 micron; 1.8 V; 2.5 Gbit/s; CMOS process; PRBS; burst-mode circuit; clock data recovery circuit; data generator; digital core; low power dissipation; pseudorandom binary sequence; Circuits; Clocks; Detectors; Ethernet networks; Hardware; Passive optical networks; Phase locked loops; Power dissipation; Power generation; Timing;
Conference_Titel :
Asian Solid-State Circuits Conference, 2005
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-9163-2
Electronic_ISBN :
0-7803-9163-2
DOI :
10.1109/ASSCC.2005.251764
