• DocumentCode
    2738139
  • Title

    Area Efficient Architecture for the Embedded Block Coding in JPEG 2000

  • Author

    Chang, Yu-Wei ; Fang, Hung-Chi ; Chen, Chun-Chia ; Chen, Liang-Gee

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
  • fYear
    2005
  • fDate
    Nov. 2005
  • Firstpage
    517
  • Lastpage
    520
  • Abstract
    An area efficient architecture for the embedded block coding in JPEG 2000 is implemented on a 1.23 mm2 die using 0.18 mum CMOS technology. This chip can support 16.7 MS/s lossless encoding. The area of the proposed architecture is only 1/6 of the conventional architectures while the throughput is the same as others. The proposed architecture has the highest performance comparing with other existing architectures according to the experimental results
  • Keywords
    CMOS integrated circuits; block codes; embedded systems; image coding; 0.18 micron; CMOS technology; JPEG 2000; area efficient architecture; embedded block coding; Arithmetic; Block codes; CMOS technology; Computer architecture; Costs; Discrete wavelet transforms; Entropy coding; Quantization; Rate-distortion; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Asian Solid-State Circuits Conference, 2005
  • Conference_Location
    Hsinchu
  • Print_ISBN
    0-7803-9163-2
  • Electronic_ISBN
    0-7803-9163-2
  • Type

    conf

  • DOI
    10.1109/ASSCC.2005.251791
  • Filename
    4017645
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2738139