Measurement of Charge Evolution in Oxides of DC Stressed MOS Structures

This work addresses electric charge measurement in gate oxides of metal-oxide-semiconductor (MOS) structures submitted to dc stress similar to that applied in power electronics components during service (2 MV/cm to 4 MV/cm). The qualitative and quantitative variation of the charge is analyzed via capacitance-voltage and thermal-step measurements, taking into account the structure geometry and the different phenomena occurring during stress. It is shown that, while the capacitance-voltage technique, which is mainly sensitive to the charges placed near the substrate, the thermal-step method is more sensitive for detecting the charges placed all over the oxide. It is shown that the association of the two complimentary techniques can allow to identify and to localize the charges across the quasi-totality of the gate oxide.