Practical design considerations for high performance MOS Σ-Δ A/D converters using cascaded second-order Σ-Δ sections

Cascading 2nd-order Σ-Δ sections to form higher order oversampling A/D converters reduces the number of comparators and the complexity of the digital circuit following the front-end required by cascading 1st-order sections. Correlated double sampling can also be arranged in 2nd order sections to suppress the 1/f noise. The op-amp output swing requirement, however, results in a 6dB loss of SNR for each cascaded 2nd-order Σ-Δ section which does not occur in cascading 1st order sections. Crucial factors limiting the Σ-Δ A/D converter resolution such as internal circuit noise and aliaing, supply noise and harmonic distortion have been discussed. A simple analytical expression is presented for estimating the op-amp swing and determining the signal and reference level. Simulation results are also presented for a quadruple integration noise shaping A/D converter designed for 64kHz baseband, 16-bit resolution and 5MHz clock frequency. The conversion speed should be much higher than the 16-bit Σ-Δ A/D converters so far reported