An expert system for mask pattern generator of CMOS logic cells

In the design of standard/macro cell VLSIs, logic cells of frequent use are generated in advance according to specified design rules and then registered in a library. If such design rules undergo changes due to renewal of fabrication process, then all registered cells have to be regenerated at the sacrifice of enormous labor and time. Thus an automatic scheme of generating such mask patterns is of practical importance. With this motivation, this paper describes a mask pattern generator for CMOS logic cells which is constructed in a knowledge-based expert system, and shows some implementation results