Computational ordering of digital networks under pipeline constraints and its application to compiler for DSPs

A digital signal processor (DSP) is a powerful device for the implementation of digital filter networks. It can implement various network structures only by changing internal instruction codes. Systems are then developed by software rather than hardware, and a DSP programmer is required to have enough knowledge of both the processor architecture and the processing algorithm to write an efficient program. The paper shows new algorithms that can determine efficient ordering of a network for the pipelined DSPs. By the use of these algorithms to the compiler, users become free from cumbersome consideration of data movements related with the pipeline, yet efficient codes are obtained