Subtractive floating-point division and square root for VLSI DSP

This paper describes recent architectural developments in VLSI design for real-time digital signal processing. In particular, floating point division and floating point square root architectures applicable to both adaptive filtering, standard deviation computations, and general purpose processing are discussed. Emphasis here is on the internal architectures of the arithmetic units not on their applications. The research presented in this paper has been proven feasible and reliable from extensive gate-level simulation and fabrication in silicon