Title :
The Optimal window-BGA Design for High-Speed SDRAM
Author :
Huang, Chih-Yi ; Cheng, Hung-Hsiang ; Wang, Chen-Chao ; Huang, Ya-Wen ; Tsun-Lung Hsieh
Author_Institution :
Electr. Lab., Adv. Semicond. Eng., Inc., Kaohsiung
Abstract :
The high performance window-BGA for a high speed Synchronous Dynamic Random Access Memory (SDRAM) has been designed. In this paper, power distribution system (PDS) design on IC package is discussed and studied. A appropriate PDS design will provide not only the stable power supply but also the superior current return path for signal channels. The simulation approach will cover complete Signal Integrity (SI) and Power Integrity (PI) analysis to quantify the electrical performance. The parasitical parameters of IC package including resistance, inductance and capacitance are extracted to check low frequency performance, and S-parameters are performed to observe the broad bandwidth response to ensure sufficient low transmission loss through entire operation frequency range. The PDS behavior in both frequency and time domain are characterized to make sure the PDS performance. Finally, eye diagram are analyzed to inspect overall electrical performance.
Keywords :
DRAM chips; S-parameters; ball grid arrays; integrated circuit packaging; power distribution; BGA; IC package; S-parameters; bandwidth response; capacitance; eye diagram; high speed synchronous dynamic random access memory; high-speed SDRAM; inductance; operation frequency; power distribution system; power integrity analysis; resistance; signal integrity analysis; transmission loss; Analytical models; Electric resistance; Frequency; Integrated circuit packaging; Performance analysis; Power distribution; Power supplies; SDRAM; Signal analysis; Signal design;
Conference_Titel :
Microsystems, Packaging, Assembly & Circuits Technology Conference, 2008. IMPACT 2008. 3rd International
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3623-1
Electronic_ISBN :
978-1-4244-3624-8
DOI :
10.1109/IMPACT.2008.4783810