Title :
A 256 Meg SDRAM BIST for disturb test application
Author :
Powell, Theo J. ; Hii, F. ; Cline, Dan
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
The Disturb Test Algorithms are targeted for row adjacent coupled defects that can be time elapsed dependent. A BIST design is described for application of these tests for testing 256 Meg SDRAM chips
Keywords :
DRAM chips; built-in self test; fault location; integrated circuit testing; memory architecture; BIST design; SDRAM BIST; address signal multiplexing; disturb test application; memory test; row adjacent coupled defects; time elapsed dependent defects; Automatic testing; Built-in self-test; Costs; Counting circuits; Geometry; Instruments; Random access memory; SDRAM; Timing; Writing;
Conference_Titel :
Test Conference, 1997. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-4209-7
DOI :
10.1109/TEST.1997.639614
