• DocumentCode
    2739013
  • Title

    A 256 Meg SDRAM BIST for disturb test application

  • Author

    Powell, Theo J. ; Hii, F. ; Cline, Dan

  • Author_Institution
    Texas Instrum. Inc., Dallas, TX, USA
  • fYear
    1997
  • fDate
    1-6 Nov 1997
  • Firstpage
    200
  • Lastpage
    208
  • Abstract
    The Disturb Test Algorithms are targeted for row adjacent coupled defects that can be time elapsed dependent. A BIST design is described for application of these tests for testing 256 Meg SDRAM chips
  • Keywords
    DRAM chips; built-in self test; fault location; integrated circuit testing; memory architecture; BIST design; SDRAM BIST; address signal multiplexing; disturb test application; memory test; row adjacent coupled defects; time elapsed dependent defects; Automatic testing; Built-in self-test; Costs; Counting circuits; Geometry; Instruments; Random access memory; SDRAM; Timing; Writing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1997. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-4209-7
  • Type

    conf

  • DOI
    10.1109/TEST.1997.639614
  • Filename
    639614
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2739013