A technology independent cell generator based on graph theoretic algorithms

A system that produces MOS leaf cell layout from an arbitrary circuit netlist is presented. The system uses graph algorithms that can be applied to a wide range of layout problems. Technology independence is achieved by using a generic layout approach and not a restrictive layout style. The VIVID symbolic layout system converts the symbolic description to a mask level description thus enabling design rule independence. The paper follows a restoring logic NAND gate cell from circuit netlist to cell layout. Representations of the NAND gate and its layout at several stages are shown