Title :
Ternary CMOS sequential circuits
Author :
Wu, Xunwei ; Prosser, Franklin
Author_Institution :
Dept. of Phys., Hangzhou Univ., China
Abstract :
Threshold comparison, transmission, and union operations are discussed and used as the basis of a logic design procedure for CMOS ternary circuits. Some basic CMOS ternary circuits are used to design CMOS ternary flip-flops (tri-flops) such as the ternary latch and various master-slave tri-flops. These tri-flops have two additional binary inverse outputs with a fixed threshold. A modulo-9 up counter is presented as an example of sequential circuit design using these tri-flops.<>
Keywords :
CMOS integrated circuits; counting circuits; flip-flops; sequential circuits; ternary logic; flip-flops; logic design procedure; master-slave tri-flops; modulo-9 up counter; ternary CMOS sequential circuits; CMOS logic circuits; Flip-flops; Impedance; Ion implantation; Logic circuits; MOSFETs; Multivalued logic; Physics; Sequential circuits; Threshold voltage;
Conference_Titel :
Multiple-Valued Logic, 1988., Proceedings of the Eighteenth International Symposium on
Conference_Location :
Palma de Mallorca, Spain
Print_ISBN :
0-8186-0859-5
DOI :
10.1109/ISMVL.1988.5188
