Title :
Stacked Via Technology for Substrate
Author_Institution :
Nan Ya Printed Circuit Board Corp. (NYPCB)
Abstract :
This paper presents reliability study of stacked via technology for substrates. It is concluded that to approach product design miniature and cost reduction, stacked via design is key tendency. A reliable stacked via formation need combine with design, material set selection, and process control of via connectivity. The reliability test application of process SQC should be able for process optimization & improvement.
Keywords :
integrated circuit design; integrated circuit reliability; integrated circuit technology; integrated circuit testing; substrates; cost reduction; material set selection; product design miniature; reliability test; stacked via design; stacked via formation; stacked via technology; substrate technology; via connectivity process control; Circuit testing; Conductivity; Dielectric materials; Materials reliability; OFETs; Printed circuits; Product design; Redundancy; Space technology; Thermal stresses;
Conference_Titel :
Microsystems, Packaging, Assembly & Circuits Technology Conference, 2008. IMPACT 2008. 3rd International
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3623-1
Electronic_ISBN :
978-1-4244-3624-8
DOI :
10.1109/IMPACT.2008.4783834
