DocumentCode :
2739550
Title :
Reliability Analysis of the Panel Base Package (PBP) Technology with Enhanced Cover Layer
Author :
Yew, Ming-Chih ; Yu, Chun-Fai ; Tsai, Mars ; Hu, Dyi-Chung ; Yang, Wen-Kun ; Chiang, Kuo-Ning
Author_Institution :
Dept. of Power Mech. Eng., Nat. Tsing Hua Univ., Hsinchu
fYear :
2008
fDate :
22-24 Oct. 2008
Firstpage :
193
Lastpage :
196
Abstract :
In this study, the modified panel base package (PBP) technology with enhanced cover layer is proposed to improve packaging reliability. One cover layer which has larger Young´s modulus than the lamination material is applied to restrain the expansion/shrinkage of dielectric. The testing samples are fabricated and tested under temperature cycling. Besides, three-dimensional finite element (FE) analysis is utilized to further elucidate the physical behavior of the modified PBP structure. From the results, the reliability of solder joint is outstanding due to the application of soft filler and lamination material. In addition, an adhesive material between the chip and the cover layer is applied as the stress buffer layer of the contact via. The designed cover layer can assist metal lines resist the dragging force from solder joint, and the accumulated plastic strain of the trace/pad connecting junction is reduced as the cover layer material becomes stronger. By using the proposed structure, the accumulated stress from the coefficient of thermal expansion (CTE) mismatch can be well distributed among packaging materials. This modified PBP technology is considered as a substantial solution for cost/performance driven integrated circuit (IC) devices in the near future.
Keywords :
Young´s modulus; buffer layers; electronics packaging; finite element analysis; reliability; thermal expansion; PBPtrade; Young´s modulus; dielectric; enhanced cover layer; expansion/shrinkage; lamination material; panel base package; reliability analysis; solder joint; temperature cycling; thermal expansion; three-dimensional finite element analysis; trace/pad connecting junction; Dielectric materials; Finite element methods; Joining materials; Lamination; Materials reliability; Packaging; Soldering; Temperature; Testing; Thermal stresses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microsystems, Packaging, Assembly & Circuits Technology Conference, 2008. IMPACT 2008. 3rd International
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3623-1
Electronic_ISBN :
978-1-4244-3624-8
Type :
conf
DOI :
10.1109/IMPACT.2008.4783842
Filename :
4783842
Link To Document :
بازگشت