DocumentCode
2739608
Title
A self-test circuit for evaluating memory sense-amplifier signal
Author
Adams, R. Dean ; Cooley, Edmond S. ; Hansen, Patrick R.
Author_Institution
Thayer Sch. of Eng., Dartmouth Coll., Hanover, NH, USA
fYear
1997
fDate
1-6 Nov 1997
Firstpage
217
Lastpage
225
Abstract
An on-chip self-test circuit to evaluate an analog sense-amplifier signal for static random-access memories was designed and analyzed. This circuit augments modern test equipment to achieve accuracy not previously possible
Keywords
CMOS memory circuits; SRAM chips; automatic testing; digital simulation; integrated circuit testing; CMOS; SRAM; accuracy; analog sense-amplifier; memory sense-amplifier signal; self-test circuit; signal level compare circuit; static random-access memories; Built-in self-test; Circuit testing; Logic arrays; Random access memory; Read-write memory; Registers; Semiconductor device measurement; Signal design; Test equipment; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1997. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-4209-7
Type
conf
DOI
10.1109/TEST.1997.639617
Filename
639617
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