A High Performance Leadframe Design For Memory Application

Memory is widely used in most applications. It has the trend for larger storage and higher speed operation, but lower prices. Leadframe based package is a low cost solution for memory applications, but it always has the problem of high lead inductance. Higher power and ground pins inductance design will result in big bouncing noise and make products malfunction. Therefore, how to reduce the lead inductance is a key issue for a successful leadframe design. Traditional power and ground pins are individually arranged from inner die pad to outer leads. Here we proposed connection type leadframe design to reduce power and ground nets inductance. Wire length impact and lead width impact are included in this study. In this paper, we even discuss the impact of different gold wire diameters. According to the simulation results for all these impacts, we will come out the low inductance and resistance design guideline for designer´s reference.