Title :
Time Delay Control Methodology for High Speed Substrate Design
Author :
Chang, Po-Hao ; Hsieh, Bryan ; Chiang, Kevin ; Lai, Jeng-Yuan ; Wang, Yu-Po
Author_Institution :
Siliconware Precision Ind. Co., Ltd., Taichung
Abstract :
For the high speed substrate design, the synchronization of the signals is one of the most important concerns. Time delay control methodologies that are based on high speed substrate design rules which include equalizing differences between the same group high speed transmission lines, maximizing time balance between different high speed transmission lines and balancing over all nets difference between every high speed transmission lines. In this paper, we consider approaches that include ground trace impacts, near by differential pairs, and reference ground plane edging to minimize the time delay between traveling signals through different high speed propagation paths. We also propose the design guidelines to minimize the time delay of signal paths. The rules are applied to high speed differential pair design FCBGA, and the time delay is controlled within 3 pico seconds.
Keywords :
ball grid arrays; delays; flip-chip devices; synchronisation; transmission lines; FCBGA; differential pairs; high speed differential pair design; high speed propagation paths; high speed substrate design; high speed transmission lines; reference ground plane; signal synchronization; time delay control methodology; Capacitance; Delay effects; Distributed parameter circuits; Guidelines; Industrial control; Integrated circuit interconnections; Integrated circuit packaging; Signal design; Strips; Transmission lines;
Conference_Titel :
Microsystems, Packaging, Assembly & Circuits Technology Conference, 2008. IMPACT 2008. 3rd International
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3623-1
Electronic_ISBN :
978-1-4244-3624-8
DOI :
10.1109/IMPACT.2008.4783863