Thermal Solutions for Multi-chip Chip Scale Packages

With the need for more functionality smaller form factor and lower cost products in electronic industry, various structures of chip scale packages (CSP) and multi-chip 3D packages have become more and popular. Compared to single die package, the multiple chips package can accommodate with multi-functional devices and increase the memory capacity within same footprint as a single die package. However, such high performance structures also result in high power consumption, which becomes a primary challenge for heat management. In this paper, we provide a thermal evaluation for multiple chips packages were considered for different package structures, and PCB design by using computational fluid dynamics (CFD) modeling technique. There are three different package structures that mounted with four dies as shown in Figural were discussed in this paper including No lead Bump Array QFN package (NBA-QFN), Exposed Pad Low Profile Quad Flat package (E-pad LQFP) and Thin Fine pitch Ball Grid Array package (TFBGA). Moreover, thermal performance for multiple chips packages with real application setting of external heat sink was also investigated. Finally, NBA-QFN package with multi-chip module thermal characteristic experiments was also conducted and had good agreement with simulation results.