A symbolic simulation-based ANSI/IEEE Std 1149.1 compliance checker and BSDL generator

Author

Singh, Harbinder ; Patankar, Girish ; Beausang, James

Author_Institution

Synopsys Inc., Mountain View, CA, USA

fYear

1997

fDate

1-6 Nov 1997

Firstpage

256

Lastpage

264

Abstract

The paper shows how to extract the boundary-scan circuitry from an IC (Integrated Circuit), verify its compliance to IEEE Std 1149.1 and generate its BSDL (Boundary Scan Description Language) description. This work applies to the 75% of boundary-scan ICs that have hand-generated or macro-cell based boundary-scan circuity. It also applies to boundary-scan ICs designed using RTL (Register Transfer Level) synthesis

Keywords

ANSI standards; IEEE standards; automatic test software; boundary scan testing; high level languages; high level synthesis; integrated circuit testing; logic testing; ANSI/IEEE Std 1149.1 compliance checker; BSDL generator; Boundary Scan Description Language; IC testing; RTL synthesis; boundary-scan circuitry; hand-generated boundary-scan circuity; macro-cell based boundary-scan circuity; register transfer level synthesis; symbolic simulation; Automatic testing; Built-in self-test; Circuit simulation; Circuit testing; Integrated circuit synthesis; Integrated circuit testing; Logic testing; Registers; Signal synthesis; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1997. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-4209-7

Type

conf

DOI

10.1109/TEST.1997.639621

Filename

639621