3D Integration : a technological toolbox

Today 3D integration technology is investigated at every microelectronic device fabrication stage. Semiconductor layers, transistors, wafers and chips are stacked to create new functionalities, enhance device performance or develop innovative systems on a chip. 3D integration technology enables bringing them together on one chip. This can be done either as a sequence of bonding and processing stages or by the bonding of dies processed in parallel. Several different approaches have been developed in order to perform 3D integration. In order to enable the full range of 3D devices from heterogeneous systems packaging to high density via IC stacking, LETI has developed key integration stages and implemented them in 3D demonstrator devices. In this paper, the generic toolbox developed at LETI is described. Several key technologies developed for parallel medium and high density 3-D integration for circuit or chip stacking are reviewed. Direct oxide or copper bonding technology, micro insert technology, die-to-wafer self-assembly, wafer thinning process and copper TSV process are discussed. New developments in sequential 3D approach are also presented.