An Efficient Implementation of SHA-1 Hash Function

The latest cryptographical application demands in a typical embedded system demand both high speed and small area. Hash function has been widely used in the digital signature, message authentication. In this paper, a new area efficient SHA-1 implementation is proposed. The proposed design was captured using VHDL hardware language and also implemented on Xilinx FPGA. The correctness of the functionality has been verified using simulation tools and the test vectors. A comparison between the proposed SHA-1 hash function implementation with other related works show that it occupies very small area while also achieving a high throughput, thus it could be adopted in an embedded system where area constraint is a concern