Title :
An Efficient Implementation of SHA-1 Hash Function
Author_Institution :
Dept. of Eng., Indiana Univ. Purdue Univ. Fort Wayne, IN
Abstract :
The latest cryptographical application demands in a typical embedded system demand both high speed and small area. Hash function has been widely used in the digital signature, message authentication. In this paper, a new area efficient SHA-1 implementation is proposed. The proposed design was captured using VHDL hardware language and also implemented on Xilinx FPGA. The correctness of the functionality has been verified using simulation tools and the test vectors. A comparison between the proposed SHA-1 hash function implementation with other related works show that it occupies very small area while also achieving a high throughput, thus it could be adopted in an embedded system where area constraint is a concern
Keywords :
cryptography; embedded systems; field programmable gate arrays; hardware description languages; SHA-1 hash function; VHDL hardware language; Xilinx FPGA; embedded system; Algorithm design and analysis; Authentication; Cryptography; Emulation; Hardware; Manufacturing; Portable computers; Protection; Security; Turning;
Conference_Titel :
Electro/information Technology, 2006 IEEE International Conference on
Conference_Location :
East Lansing, MI
Print_ISBN :
0-7803-9592-1
Electronic_ISBN :
0-7803-9593-X
DOI :
10.1109/EIT.2006.252210
