Title :
SOI at IBM: current status of technology, modeling, design, and the outlook for the 0.1 μm generation
Author :
Assaderaghi, Fari ; Shahidi, Ghavam
Author_Institution :
Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA
Abstract :
This paper reviews the evolution of partially depleted (PD) CMOS SOI technology at IBM. Several aspects of this development leading to successful fabrication of high-performance microprocessors are discussed. They include SOI-specific device design and process modifications; creation of compact device models for circuit simulation (SPICE-like models); and development of circuit styles and strategies employed in the design of CMOS VLSI on PD SOI. Since these strategies address issues and problems that arise on PD SOI circuits such as delay hysteresis, and noise margin reduction, they are discussed in detail. The discussion is focused on the 0.18 μm and 0.13 μm generations, with some deliberations on the 0.10 μm node
Keywords :
CMOS integrated circuits; SPICE; VLSI; circuit simulation; delays; hysteresis; integrated circuit modelling; integrated circuit noise; integrated circuit technology; microprocessor chips; silicon-on-insulator; 0.1 micron; 0.13 micron; 0.18 micron; IBM; PD SOI CMOS VLSI design; PD SOI circuits; SOI; SOI design; SOI modeling; SOI technology; SOI-specific device design; SOI-specific process modifications; SPICE-like models; Si-SiO2; circuit simulation; circuit styles; compact device models; delay hysteresis; design strategies; microprocessors; noise margin reduction; partially depleted CMOS SOI technology; technology generations; CMOS process; CMOS technology; Circuit simulation; Delay; Fabrication; Hysteresis; Microprocessors; Process design; Semiconductor device modeling; Very large scale integration;
Conference_Titel :
SOI Conference, 2000 IEEE International
Conference_Location :
Wakefield, MA
Print_ISBN :
0-7803-6389-2
DOI :
10.1109/SOI.2000.892743
