DocumentCode
2740533
Title
Impact of parameter variations on FinFET faults
Author
Harutyunyan, G. ; Tshagharyan, G. ; Zorian, Y.
Author_Institution
Synopsys, USA
fYear
2015
fDate
27-29 April 2015
Firstpage
1
Lastpage
4
Abstract
The technology shrinking strategy below 20nm feature sizes adopted by the giants of the nowadays semiconductor industry has boosted the research on FinFET which is considered as an alternative to the conventional planar technology. This paper presents a comprehensive study carried out for FinFET-based memories using an advanced flow for fault modeling and test algorithm generation. Using this flow it has been shown that parameter variation (of process, voltage, temperature, frequency) has a significant impact on the fault coverage when dealing with FinFET-specific faults.
Keywords
MOSFET; integrated memory circuits; semiconductor device models; semiconductor device reliability; semiconductor device testing; semiconductor industry; FinFET-based memories; FinFET-specific faults; fault coverage; fault modeling; planar technology; semiconductor industry; technology shrinking strategy; test algorithm generation; FinFETs; Foundries; Logic gates; Resource description framework; Temperature sensors; FinFET; embedded memory; fault modeling; parameter variation; test algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium (VTS), 2015 IEEE 33rd
Conference_Location
Napa, CA
Type
conf
DOI
10.1109/VTS.2015.7116276
Filename
7116276
Link To Document