Title :
Fault-Tolerant Circuit for Carbon Nanotube Transistors with Si-CMOS Hybrid Circuitry
Author :
Yasuda, Shinichi ; Akinwande, Deji ; Close, Gael F. ; Wong, H. S Philip ; Paul, Bipul C. ; Fujita, Shinobu
Author_Institution :
Adv. LSI Technol. Lab., Toshiba Corp., Kawasaki
Abstract :
This paper presents the concept of a robust hybrid circuit in which reliable Si-CMOS circuits support the unreliable carbon nanotube-based circuit. We fabricated a test circuit and demonstrated the recovering operation from timing errors caused by delay variation of carbon nanotube transistors. We also estimated the overhead of the hybrid circuit, and confirmed by simulation that the delay overhead of the Si-CMOS part is small compared to the total delay.
Keywords :
CMOS integrated circuits; carbon nanotubes; elemental semiconductors; fault tolerance; field effect transistors; integrated circuit testing; monolithic integrated circuits; nanotube devices; silicon; C-Si; carbon nanotube field effect transistors; delay; fault-tolerant circuit; robust hybrid circuit; silicon-CMOS hybrid circuitry; timing errors; Carbon nanotubes; Circuit faults; Clocks; Delay estimation; Fault tolerance; Frequency; MOSFETs; Ring oscillators; Timing; Voltage;
Conference_Titel :
Nanotechnology, 2008. NANO '08. 8th IEEE Conference on
Conference_Location :
Arlington, TX
Print_ISBN :
978-1-4244-2103-9
Electronic_ISBN :
978-1-4244-2104-6
DOI :
10.1109/NANO.2008.207
