Title :
An efficient approach to constrained via minimization for two-layer VLSI routing
Author :
Tang, Maolin ; Eshraghian, Kamran ; Cheung, Hon Nin
Author_Institution :
Centre for Very High Speed Microelectron. Syst., Edith Cowan Univ., Perth, WA, Australia
Abstract :
Constrained via minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate
Keywords :
VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; minimisation; network routing; IC layout; constrained via minimization; two-layer VLSI routing; wire segments; Australia; Fabrication; Heuristic algorithms; Integrated circuit yield; Joining processes; Microelectronics; Minimization; Routing; Very large scale integration; Wire;
Conference_Titel :
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Conference_Location :
Wanchai
Print_ISBN :
0-7803-5012-X
DOI :
10.1109/ASPDAC.1999.759982
