DocumentCode :
2741036
Title :
Acceleration of linear block code evaluations using new reconfigurable computing approach
Author :
Nagano, Hidehisa ; Suyama, Takayuki ; Nagoya, Akira
Author_Institution :
NTT Commun. Sci. Labs., Kyoto, Japan
fYear :
1999
fDate :
18-21 Jan 1999
Firstpage :
161
Abstract :
This paper presents an approach to performing applications using reconfigurable computing (RC). Our RC approach is achieved by effective use of design automation systems. Logic circuits specialized for each individual application task are automatically implemented on FPGAs. Such circuits can quickly perform tasks that are time-consuming for general purpose computers. Decoding of binary linear block codes for the evaluation is taken up as an example application. Experimental results show that the time for decoding of the code specific decoding circuit implemented on FPGAs, in which computations are executed in parallel, is much shorter than that of the software decoder
Keywords :
block codes; decoding; field programmable gate arrays; linear codes; logic CAD; FPGAs; binary linear block codes; code specific decoding circuit; design automation systems; linear block code evaluations; logic circuit implementations; reconfigurable computing approach; Acceleration; Application software; Block codes; Circuit synthesis; Computational modeling; Concurrent computing; Decoding; Design automation; Field programmable gate arrays; Logic circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Conference_Location :
Wanchai
Print_ISBN :
0-7803-5012-X
Type :
conf
DOI :
10.1109/ASPDAC.1999.759985
Filename :
759985
Link To Document :
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