Co salicide technology for sub-0.15 μm FD-SOI and beyond: super-flat silicide and fully-silicided source/drain structure

Fully-depleted SOI devices have excellent characteristics for low power applications, in such regards as low subthreshold swing, low source/drain (S/D) capacitance and small floating body effect compared to bulk devices or partially-depleted SOI devices (Imai et al, 1998; Chen et al, 1999). These features derive from the thin SOI layer whose typical thickness is less than 50 nm; however, silicidation of such thin SOI films makes device fabrication extremely difficult. In order to keep sheet resistance low enough even in narrow lines many methods have been proposed to date, but they are not applicable to FD-SOI devices because FD-SOI devices require much higher silicide uniformity. Another important issue to overcome is reduction of the parasitic source/drain series resistance. This work presents a solution for such ultra-thin SOI layers in the fabrication of ULSI devices. The new salicide is applied to the fabrication of sub-0.20 μm FD CMOS devices on ultra-thin SOI substrates to investigate the validity of the FD-CMOS structure where S/D Si is completely consumed (fully silicided)