Back gate engineering for suppression of threshold voltage fluctuation in fully-depleted SOI MOSFETs

Author

Numata, T. ; Noguchi, M. ; Oowaki, Y. ; Takagi, S.

Author_Institution

Lab. for Adv. LSI Technol., Toshiba Corp., Yokohama, Japan

fYear

2000

fDate

2000

Firstpage

78

Lastpage

79

Abstract

Threshold voltage fluctuation due to SOI thickness variation is one of the most serious problems in fully-depleted (FD) SOI MOSFETs. In order to suppress this threshold voltage (V_th) fluctuation in FD SOI-MOSFETs, we propose a new back gate engineering scenario in which the back gate is biased in order to make the back interface of SOI films weakly accumulated, under very thin buried oxides allowing strong coupling between back gate and Si films. It is shown theoretically and experimentally that this back gate engineering significantly reduces the V_th fluctuation, because of the balance between the amount of space charge in SOI films and the electric field at the front surface of the SOI films

Keywords

MOSFET; buried layers; electric fields; semiconductor device measurement; silicon-on-insulator; space charge; FD SOI MOSFETs; FD SOI-MOSFETs; SOI films; SOI thickness variation; Si-SiO₂; back gate bias; back gate engineering; back gate-Si film coupling; electric field; fully-depleted SOI MOSFETs; space charge; thin buried oxides; threshold voltage fluctuation; threshold voltage fluctuation suppression; weakly accumulated SOI film back interface; Analytical models; Capacitance; Fluctuations; Laboratories; Large scale integration; MOSFETs; Research and development; Semiconductor films; Space charge; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2000 IEEE International

Conference_Location

Wakefield, MA

ISSN

1078-621X

Print_ISBN

0-7803-6389-2

Type

conf

DOI

10.1109/SOI.2000.892778

Filename

892778