Title :
Research on the Low Power Dissipation of Pipeline ADC
Author :
Li, Bo ; Li, Zheying ; Chen, Tingting
Author_Institution :
Beijing Jiaotong Univ., Beijing
Abstract :
A design of 50 MHz, 10 bits, 5 V pipeline ADC is introduced in this thesis. The comparator and OTA are the main improvements aiming at realizing low power dissipation. The dynamic comparator and telescopic OTA are adopted to achieve the specification. The design is implemented under 0.5 mum CMOS technology which achieves a power dissipation of 190 mW at 50 MHz sampling rate.
Keywords :
CMOS integrated circuits; analogue-digital conversion; pipeline processing; CMOS technology; low power dissipation; pipeline ADC; CMOS technology; Circuit noise; Clocks; Latches; Pipelines; Power dissipation; Sampling methods; Space technology; Switches; Voltage;
Conference_Titel :
Innovative Computing, Information and Control, 2007. ICICIC '07. Second International Conference on
Conference_Location :
Kumamoto
Print_ISBN :
0-7695-2882-1
DOI :
10.1109/ICICIC.2007.488
