DocumentCode
2741144
Title
Research on the Low Power Dissipation of Pipeline ADC
Author
Li, Bo ; Li, Zheying ; Chen, Tingting
Author_Institution
Beijing Jiaotong Univ., Beijing
fYear
2007
fDate
5-7 Sept. 2007
Firstpage
498
Lastpage
498
Abstract
A design of 50 MHz, 10 bits, 5 V pipeline ADC is introduced in this thesis. The comparator and OTA are the main improvements aiming at realizing low power dissipation. The dynamic comparator and telescopic OTA are adopted to achieve the specification. The design is implemented under 0.5 mum CMOS technology which achieves a power dissipation of 190 mW at 50 MHz sampling rate.
Keywords
CMOS integrated circuits; analogue-digital conversion; pipeline processing; CMOS technology; low power dissipation; pipeline ADC; CMOS technology; Circuit noise; Clocks; Latches; Pipelines; Power dissipation; Sampling methods; Space technology; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Innovative Computing, Information and Control, 2007. ICICIC '07. Second International Conference on
Conference_Location
Kumamoto
Print_ISBN
0-7695-2882-1
Type
conf
DOI
10.1109/ICICIC.2007.488
Filename
4428140
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